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Spartan 6 FPGA Module


D.Module2.6SLXT is a Spartan 6 FPGA Module, and modular component of the D.Module2 embedded DSP product family - intended for use with D.moudule2 embedded DSP boards and systems.

The Spartan 6 LXT FPGA can be programmed to interface with and pre-process data from high speed, high bandwidth peripheral interfaces, relieving the DSP of unnecessary overhead.

Spartan 6 FPGA Module - D.Module2.6SLXT

With the Spartan 6 handling high bandwidth activities, lower bandwidth postprocessing, analysis, and algorithm control can then be more conveniently performed by the DSP processor . Additionally the FPGA can potentially implement supplemental peripherals, such as PWM controllers, frame grabbers, CAN Bus controllers, etc.

Peripherals and data acquisition subsystems can be connected to the FPGA through a maximum of 98 user definable single-ended signals (48 LVDS signal pairs), and up to three Gigabit links. These I/Os conform to the industry standard VITA 57 FMC specification. A suitable prototyping platform, the D.Module2.Base-FMC, providing an an FMC LPC mezzanine site together with accommodation for a D.Module2 stack.

The DSP is by default connected to the FPGA via the D.Module2 32-bit wide parallel bus interface. Depending on the DSP capabilities alternative data paths exist: Serial Rapid IO (SRIO) on the GTP connector and LVDS (e.g. TigerSHARC® Link Ports) on the EXP connector. The EXP signals are available as free user-programmable I/O if not used for DSP-FPGA communication, e.g. as a base mode CameraLink.

The Spartan 6 GTPs (Gigabit Transceivers) provide additional high-speed connectivity interfaces like SRIO for inter-board communications, JESD204/A as a high-speed A/D and D/A interface, SGMII to interface a Gigabit Ethernet PHY, SATA, DisplayPort 1.1, and PCIe v1.1.

The DSP has full access to the FPGA configuration Flash Memory and can re-configure and update the FPGA at any time. Other key features are programmable I/O voltage, 128M Bytes local DDR3 RAM and a JTAG interface for FPGA programming and debugging via Xilinx ChipScopeTM.

Product Features

FPGA Xilinx Spartan6
Default FPGA Type: XC6SLX45T
Optional FPGA Type: XC6SLX100T
logic cells 43661 101261
flip flops 54576 126576
logic slices 6822 15822
DSP48A1 slices 58 180
clock manager 4 6
block RAM 2088k bit 4824k bit
GTP 4 4
Memory DDR3 128M Bytes, 333MHz
Configuration 8M Bytes SPI Flash Memory
Clock Resources external BUSCLK (from DSP module)
4 single-ended (2 LVDS) global clock nets on EXP connector
12 single-ended (6 LVDS) clock nets on BUS1 and BUS2 connectors
2 LVDS reference clocks for Gigabit Transceivers
internal programmable clock synthesizer AUXCLK
two reference clocks for Gigabit Transceivers
DSP Interface Parallel Bus 32 data bits, 20 address lines, 10 control lines, synchronous pipelined and/or asynchronous operation (depending on DSP capabilities)
LVDS 8 data lines, 2 clocks, 2 control lines (e.g. Link Ports on D.Module2.TS203)
usable as additional User-I/O if not used for DSP-FPGA communications.
SRIO one lane, up to 3.125Gb/s
Misc. 4 GPIO
3 Interrupts
2 Serial Ports
Gigabit Transceivers 4 one routed to top connector (DSP SRIO interface),
3 on bottom side connector for User-I/O, supporting PCIe (1x, v1.1), SGMII, JESD204/A, SATA, SRIO, DisplayPort 1.1
User I/O default 74 single-ended / 36 LVDS, VITA 57 FMC compatible
maximum 98 single-ended / 48 LVDS if EXP signals not used for DSP interface
I/O Voltage programmable 1.8, 2.5, 3.3V
Power Supply 3.3V single supply
Mechanics 87 x 58 x 15 mm self-stacking design, board-spacing 10mm
IEEE-1386 high-density connectors
RoHS conformity yes